1. Field of the Invention
The present invention generally relates to application specific integrated circuits (ASIC) and to a method for communications, and more particularly, to a logic device for facilitating an interface between logic circuits operating at two differing clock domains.
2. Description of the Related Art
Typically, computer hardware includes various data buses for transmitting data from one device to another. For example, a personal computer (PC) may have a main bus, a local bus, a video bus, etc. A computer server typically includes multiple microprocessors and data buses. Should a first device (e.g., a processor) on one bus need to communicate to a second device (e.g., a graphic's adapter) on another bus, an interface, such as a bridge, is employed to transfer the data seamlessly from one bus to another, and vice versa, if needed.
At times, the various computer buses may operate at different clock rates. For example, one of the local buses, such as a PCI (and its derivatives, PCI-X) may operate at 66 MHz, 100 MHz or 133 MHz and a legacy local bus, such as an ISA bus may operate at 8 MHz. Another example includes buses within an ASIC chip, such as an Inter Module Bus (IMB), which may operate at a higher frequency than a PCI (or PCI-X) bus, such as 200 MHz.
A prior method for coupling logic circuits operating at different frequencies (e.g., a first logic circuit operating at 100 MHz coupled to a second logic circuit operating at 50 MHz) includes an interface that would create a stretched version of a signal from the first logic circuit that was long enough to be detected by the second logic circuit. That is, the first logic circuit would send signals that are 10 nanoseconds long. But since the second logic circuit operates at 50 MHz, the second logic circuit would generally not be able to detect the signals since the second logic circuit would typically be able to detect signals that are 20 nanoseconds or longer. Consequently, the prior method would stretch a signal in time by resending the signal (signals transmitted in consecutive clock cycles). Thus, this prior method requires knowledge of the clock frequency domains for each logic circuit so that the interface can be designed to provide the necessary signal between the logic circuit. In addition, this prior method typically utilized logic that is inflexible to changing circumstances. That is, prior interfaces were designed to operate between particular logic circuit operating at known particular frequencies. Consequently, these interfaces generally could not be used with logic circuits operating at other frequencies that they were not designed for.
In addition, the prior method is typically limited by a frequency ratio. As mentioned above, interfaces used in prior methods are generally designed to handle a particular frequency ratio, e.g., 3:1. Thus, the frequency domain on one side could not be greater than 3 times the frequency of the other side. Furthermore, the prior method typically requires more logic to implement, thus requiring more precious silicon real estate.